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Why cram the limit of small into one little corner?
Spacing the transistors out, relatively speaking, means they are smaller compared to transistors in the densely packed standard package.Also, there seems a lot of space getting CPU connection pins down to the transistor size in the CPU package.There
might even be a cooling advantage in spacing transistors.
Warning: Plugging in that volumetric tower CPU for that work critique may offend.
(?) Slower can be smarter.
https://twitter.com...1159694548278185984
How does one escape the inertia of the group to gain a better difference? [wjt, Aug 11 2019]
[link]
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But if transistors are further apart signals take longer to travel between them |
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It is a remarkable world where we're up against speed-of-light
delays between micron-sized components. Surely, the
development of the first real computer cannot be far off. |
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//micron-sized components//
Not anymore they're not |
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// Surely, the development of the first real computer cannot be far off.// |
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must not bite, must not bite |
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Thought this might be an idea for a method to
increase the distance between each chip in a
portion of fish and chips. |
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No, you make the chips from aerated potato pulp. Higher ratios of aer to potatoe makes the chips less dense and reduces raw material cost. |
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//Higher ratios of aer to potatoe // That reads as if it should
be read in a pirate voice. |
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"Chicken pieces of eight ... chicken pieces of eight ..." |
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I wonder if computers could be made faster with a sort of
"catch up" programming. |
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For instance, a group of computer gates is waiting for an
input, and will then compute to give an output. But it takes a
while for that input to reach the gates. So, have the gates
calculate the output for either possible input and then, by the
time the input actually arrives, they can just output the
appropriate precalculated result. |
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Can't transistors be 3D though. An example would be an OR gate that raises a circuit going up one layer if true and raises a circuit going down if false as well as the standard output on the horizontal layer. Trees of circuits across and up and down. |
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More space opens up more connective branches.The minimum limit would be a 3x3x3 cube of transistors: 1 input , 25 outputs or 25 inputs, 1 output.
Give an AI the components and see what it builds. |
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// have the gates calculate the output for either possible input and then, by the
time the input actually arrives, they can just output the appropriate
precalculated result. // |
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// Yes, that was done several years ago (2003 for first WP article) - predictive
branching. // |
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But that's on the level of instructions, not the level of logic gates. On the other
hand, I don't think there would necessarily be any speedup from doing this on the
gate level. If the gate or network of gates precomputes outputs for all possible
combinations of inputs, the propagation delay to choose which of those outputs
to give when the input arrives is probably the same as the propagation delay of
actually computing the output. And, assuming you don't throw away and
recompute this set of outputs between every presentation of inputs and the next
one (which seems like a silly thing to do), you've essentially turned your gate(s)
into a LUT—which is already known to be able to stand in for any arrangement of
gates with a given number of inputs and outputs anyway. |
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I suppose, if it turns out that a LUT is somewhy faster than actual gates in a given
application (a long cascade of gates?), you could have the actual gates compute
the output when a not-seen-before input is given, and store that in the LUT for
next time. But then you need a writeable LUT, which is more expensive (in
money, die space, and power) than a read-only one, and has no advantage over a
read-only one except in cases where a read-only one would have to be
impractically large, in which case a smaller but writeable one in parallel with
actual gates would have an advantage, but only for a subset of recently seen
inputs (i.e. a memoization cache considerably smaller than the set of all possible
inputs). But then you need additional processing of some sort (more gates?) to
manage what stays in the cache and what gets thrown out, unless you've invented
some sort of automatic-cache-managing ram that exploits physical principles to
track what data is least recently used, or something like that. |
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So what I am really saying is that is seems computer is making more by packing smaller of the same dimensional method rather than using the space, which as [hippo] indicated is time, to create a computing advancement of higher dimensions. |
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Well, apparently there are another 7 dimensions curled up
really small. We should probably fill them up. |
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We probably already do. No? |
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I was thinking, cars and roads could be a really ruff analogy to chip circuits.The cars all following logic making overall patterns. If it was now said that red cars had to make left turns and blue cars only right turns to destinations, is this adding another dimension? |
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// Well, apparently there are another 7 dimensions curled
up really small. We should probably fill them up. // |
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That's how sophons work. I wonder how sophons get energy,
and dispose of waste energy. |
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//If it was now said that red cars had to make left turns and blue cars only right turns to destinations, is this adding another dimension?//
I think this would just lead to people getting out of their cars and respraying them by the side of the road in order to get to their destination faster. Or I suppose you could have two cars, red and blue, one on a trailer towed behind the other. Then when you wanted to change the direction you were allowed to turn you'd just have to stop and swap the cars over, covering up the towed car with a tarpaulin, of course. |
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It is always the case, the weighing up of the time it takes to circumvent a rule, with consequences, and the time of just doing the rule. |
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I never did get that folded up dimension thing. Either you have 7 dimensions or you don't. |
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