FPGA coprocessor

What it is, is essentially a upgradable FPGA coprocessor placed in a ZIF socket near the CPU.

Instead of always having to upgrade the CPU or the GPU for the next 'GPGPU' features, just have the program itself carry some netlist that they can use to accelerate themselves.

The benefit of this approach is that it allows for the program to create virtual hardware optimized specifically to solve its problem. Which would be much faster than the normal CPU, or even the 'shaders' in a GPU that tends to be oriented towards graphical problems.

It also future proofs the computer to a certain extent as long as you standardize the FPGA coprocessor, programming interface (so the first 10 pins can be specifically to reconfigure the processor, at each run), and liberally add excessive number of pins (not all has to be used). This is because the pins of the FPGA coprocessor can be reconfigured at will anyway.

Another cool feature of this processor is you can still apply multitasking to this, as there may either be enough floorspace for multiple different circuits for each program. Or you can quickly refresh the FPGA with different circuits every microseconds or so. (inspired by some company who is promoting an FPGA that simulates more gates than it has, by remembering each layers and flipping though each quickly)

It is also highly future proofed, since as long as you keep the programming procedure, protocol and the slot the same. You can still upgrade your old computer 5 years down the track, when they have FPGAs with 90000x the gates we currently have for our top end FPGAs.

REAL WORLD USAGE: You can decode the latest video, even if you don't have the latest 'Shader DX 90000000000' for your GPGPU enabled graphics card to process it fast enough.